1. Field
The present disclosure relates to programmable logic arrays (PLAs). In particular, it relates to PLA clusters and interconnections thereof.
2. Related Art
Before lithographic integrated circuits, logic was “customized” by discrete wiring (e.g. patch cables). Once lithography could support enough logic on a single chip to accommodate programmable configuration elements, it became useful to include memory elements which could configure the state of the device. As a result PALs (Programmable Array Logic), PLDs (Programmable Logic Devices), and ultimately FPGAs (Field Programmable Gate Arrays) were developed.
A PLA is a programmable device used to implement combinational logic circuits. A PLA is often said to have an “AND” plane followed by an “OR” plane. In practice, universal gates such as NAND or NOR gates are normally used. Usually, a PLA has a selective inversion capability, which makes it irrelevant whether the actual logic is NAND, NOR or AND, OR. Further, PLAs exploit DeMorgan's equivalences, so that a native NOR plane (with selective inversion) can act as a NAND plane or vice versa.
Over the past few years, many technologies have been demonstrated for molecular-scale memories. So far, they all seem to have: (1) resistance which changes significantly between “on” and “off” states, (2) the ability to be made rectifying, and (3) the ability to turn the device “on” or “off” by applying a voltage differential across the junction. An 8×8 crossbar made from rotaxane molecules has been demonstrated. It has been observed that an order of magnitude resistance difference between “on” and “off” state junctions could be forced. See, C. Collier, G. Mattersteig, E. Wong, Y. Luo, K. Beverly, J. Sampaio, F. Raymo, J. Stoddart, and J. Heath, A[2]Catenane-Based Solid State Reconfiguration Switch, Science, 289:1172-1175, 2000; C. P. Collier, E. W. Wong, M. Belohradsky, F. M. Raymo, J. F. Heath, Electronically configurable molecular-based logic gates, Science, 285:391-394, 1999.
Consequently, simple and manufacturable way of integrating restoration with programmability, and manufacturable techniques which allow wires to be tightly packed at nanoscale pitches and allow the nanoscale crosspoints to be addressed from microscale wires have been shown in U.S. patent application Ser. No. 10/856,115, filed May 28, 2004 for “Nanoscale Wire-Based Sublithographic Programmable Logic Arrays” by Andre' DeHon and Michael J. Wilson, the disclosure of which is incorporated herein by reference in its entirety.
When building large nanoPLAs, the wires in the nanoPLAs will become very long. Long nanowires are difficult to manufacture without defects and can be very slow. In particular, the nanoscale diameter wires tend to break during assembly when their length becomes many tens of microns in length. Further, the resistance of the small diameter nanowires becomes larger with the length of the nanowires making PLA operation slower.
Therefore, there is a need to be able to build large logic designs at the nanoscale while keeping the lengths of individual nanowires relatively short.
One way to build large logic is to provide interconnect between small or modest-sized logic clusters. In this way, the wires in each clusters and the wires among clusters can be kept short while the interconnected set of logic clusters implements a large logic function.
Consequently, the present application discloses how to build nanoscale PLA logic clusters and interconnect them with nanoscale interconnect. The resulting interconnected PLAs can implement arbitrary sized logic or finite-state machines while using modest-sized PLAs and moderately short nanowires. Further, the nanoscale PLA and nanoscale interconnect can all be constructed using bottom-up assembly techniques to determine the nanoscale features and provide the tight, nanoscale pitches for logic, restoration, and interconnect.